Automatic test equipment (ATE) is universally used to test semi-conductor chips and integrated circuits during their manufacture. Functional testing is typically performed by configuring the ATE to apply electrical signals to numerous connection points on the device under test (DUT) while measuring the output response of the DUT at certain connection points.
ATE typically determines the relative timing between applied input signals and measured output signals when evaluating the performance of a DUT. Very accurate timing of the test system clock is often required to ensure that appropriate data is collected, particularly when evaluating a DUT's response to high speed signals.
It is often desirable to test the performance of a DUT relative to its own system clock. Accordingly, ATE can typically be configured to measure output at times relative to the DUT's internal clock. However, measurements relative to the DUT's system clock can be inaccurate at high data rates and clock speeds because signal slewing and jitter significantly affect measurement results.
Many integrated circuits (ICs) now include buses with a synchronous clock that accompanies the data. It is impractical to access a DUT's synchronous internal clock without tying up valuable test system hardware channels. It has also heretofore been problematic to use a test system clock to test data on buses having a synchronous clock because data on the bus may have very high jitter relative to the test system clock.
A method and apparatus which uses a test system clock to emulate the DUT clock for comparison with DUT data signals without suffering the excessive slew and jitter usually associated with use of the system clock is described in Applicant's co-pending U.S. patent application Ser. No. 11/234,542 entitled “Strobe Technique for Test of Digital Signal Timing” filed Sep. 23, 2005, which is incorporated herein by reference.
In systems having clock information imbedded in a digital signal, it is often desirable to recover the clock information for testing purposes. In the field of ATE, for example, it is often desirable to recover clock information that is imbedded in a digital signal that is received from a DUT. Clock information has heretofore typically been recovered from digital signals by using phase-locked loop PLL based clock recovery circuits. PLL based clock recovery circuits are disadvantageously limited to use in specific pre-set bandwidths.